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Collaboration takes Risc-V into IoT development

Steve Rogerson
December 1, 2016
At this week’s Risc-V Workshop on the Google Quad Campus in California, a US-European collaboration announced an integrated IoT development platform based on the Risc-V open processor instruction set architecture (ISA).
The four companies involved are California’s BaySand, Czech Republic-based Codasip, Scottish firm Codeplay and UltraSoC from Cambridge, UK. The platform offers an open-standards-based way for designers of systems-on-a-chip (SoCs) for IoT applications to get from concept to silicon with a high level of software integration quickly, while removing risks from the entire product development process.
It combines BaySand’s foundational IP and metal configurable standard cell (MCSC) technology, Codasip’s extensible Codix Bk Risc-V-compliant processor implementation, Codeplay’s ComputeSuite software development tools for open standards middleware, and UltraSoC’s on-chip debug and analytics architecture.
The result is an end-to-end development flow that supports the rapid evolution of IoT systems, enabling timely market entry, in-market feature enhancement and on-going usability and cost optimisation.
“Risc-V adoption is accelerating, and the IoT is clearly an arena where an open, independent processor architecture offers very powerful advantages,” said Caroline Gabriel, research director of ReThink Research. “But as with any processor architecture, the Risc-V ISA needs a healthy, cooperative ecosystem surrounding it: an ecosystem that puts designers in control and empowers innovation.”
Rick O’Connor, executive director of the Risc-V Foundation, added: “A key part of our mission at the Risc-V Foundation is to bring technology developers together, in a standards-based environment, to build a robust ecosystem around the Risc-V ISA. We’re delighted to see these four leading firms in the Risc-V community coming together.”
The platform leverages BaySand’s patented MCSC technology which delivers the power, performance and density advantages of standard cell ASIC technology while reducing NRE and time to market and dramatically increasing design flexibility. The company’s UltraShuttle multi project wafers and MetalCopy FPGA porting technology help to bring new designs to market quickly, with low risk: they combine with a proven and predictable design flow and an IP library for IoT class designs.
“BaySand is a supporter of open source hardware and we are excited to be part of this great team that brings together an open source ISA,” said Ehud (Udi) Yuhjtman, EVP at BaySand. “This Risc-V implementation with the UltraSoC tools is a game changer that will enable designers and companies to design at an affordable budget their own efficient IoT ASIC and system. We are working on the ASIC implementation, which will be available for evaluation to our customers and partners. The complete technology provides the ability to build custom designs with BaySand special UltraShuttle MPW and the MCSC.”
At the IP level, Codasip’s Codix-Bk IP cores are said to be the industry’s first commercially available Risc-V compliant processors, and are at the heart of the new joint platform. They are available in multiple configurations and can be quickly and easily customised to the exact needs of IoT designs via application analysis technology and a model-based IP structure.
“This collaboration is an important one for our customers as they look to replace proprietary ISAs with Risc-V,” said Karel Masarik, CEO of Codasip. “It allows them to quickly bring new SoCs to life, while providing functionality that exceeds what they have had access to in the past. Our Codix-Bk series of Risc-V processor IP, with its LLVM-based development environment, make integration quick and low risk, demonstrating the power of commitment to open standards.”
UltraSoC contributes silicon IP and software tools that enable secure, non-intrusive monitoring and analysis of IoT device behaviour. These features ease the task of writing and debugging the software that is intrinsic to the operation of complex ICs; they accelerate first-time bring up of new devices; and the same IP allows robust hardware-based security features that can detect unexpected behaviour caused by bugs or by malicious interference.
“We’re delighted to be coming together with three of the other key players in the Risc-V arena,” said Rupert Baines, CEO of UltraSoC. “Our aim in this collaboration is to enable accelerated product development cycles, lower costs and more agile development, in particular for IoT designs. Our technology helps SoC developers across the chip and throughout the development flow, and this partnership reinforces the strength of that offering.”
At the highest level within the platform, Codeplay provides developers with an open standards based programming model that extends from device-specific functionalities all the way up to highly abstracted machine learning paradigms such as Google’s TensorFlow. ComputeSuite extends the Risc-V platform with Open CL and SYCL allowing applications to target the underlying hardware for higher performance, using standard APIs.
“Codeplay is excited to see Risc-V gaining in popularity and we are keen to ensure software developers are correctly equipped to host their software applications on it,” said Andrew Richards, CEO of Codeplay. “Codeplay is working extensively with machine learning solutions such as Google with TensorFlow, and we will bridge the gap on Risc-V with the open standards Open CL and SYCL.”